/*Device: ROC1_UDS710
 *Version: UDS710_1_IRD_UDX710_SCH_V1.0.0_Pinmap_V1.0
 *Creat Time: 2019/01/31 14:51:38
 *Author: Yang.Ni
 */

/*
 * Copyright (C) 2012 Spreadtrum Communications Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */


#include <asm/io.h>
#include <asm/arch/pinmap.h>
#include <power/sprd_pmic/sprd_2730_pinmap.h>

#define BIT_PIN_SLP_ALL            (BIT_PIN_SLP_AP|BIT_PIN_SLP_PUBCP|BIT_PIN_SLP_WTLCP|BIT_PIN_SLP_AUDCP|BIT_PIN_SLP_CM4)
#define BIT_PIN_SLP_ALL_CP         (BIT_PIN_SLP_PUBCP|BIT_PIN_SLP_WTLCP|BIT_PIN_SLP_AUDCP|BIT_PIN_SLP_CM4)
#define BIT_PIN_SLP_ALL_NO_CM4     (BIT_PIN_SLP_AP|BIT_PIN_SLP_PUBCP|BIT_PIN_SLP_WTLCP|BIT_PIN_SLP_AUDCP)



static pinmap_t pinmap[]={
{REG_PIN_CTRL_REG0,0x00000000},//Reserved;
{REG_PIN_CTRL_REG1,0x00000000},//wdrst_out_sel -> AP watch dog;
{REG_PIN_CTRL_REG2,0x00000000},//uart_usb_phy_sel -> usb phy
{REG_PIN_CTRL_REG3,0x00000000},//SP_EIC_DPAD source select
{REG_PIN_CTRL_REG4,0x00000000},//SP_EIC_DPAD source select
{REG_PIN_CTRL_REG5,0x00104B00},//pubcp_sim0_bd_eb; pubcp_sim1_bd_eb; ap_sdio_bd_eb; ap_emmc_bd_eb; sim0_det_sel -> pubcp sim0; card_det_sel -> apsd0 card; vbc_iis_inf_sys_sel -> aon_usb_audio_iis;

//{REG_PIN_PWR_PAD_CTL_RESERVED,0x00000000},
//UART3
{REG_PIN_UART_MATRIX_MTX_CFG,0x06000806},//UART0->AUDDSP_UART0; UART1->AP_UART1; UART2->PUBCP_UART0; UART3->wtlcp_wci2; UART4->AP_UART0; UART5->CM4_UART0; UART6->TGDSP_UART0;
{REG_PIN_UART_MATRIX_MTX_CFG1,0x0000002B},//UART7->PUBCP_UART1; UART8->AP_UART2;
{REG_PIN_IIS_MATRIX_MTX_CFG,0x00019040},//IIS0->AP_IIS0; IIS1->AP_IIS1; IIS2->AP_IIS2; IIS3->PUBCP_IIS0;
{REG_PIN_SIM_MATRIX_MTX_CFG,0x00000002},//SIM0->PUBCP_SIM0; SIM1->PUBCP_SIM1; SIM2->AP_SIM0;
{REG_PIN_SPI_MATRIX_MTX_CFG,0x00000000},//SPI0->AP_SPI0; SPI1->AP_SPI1; SPI2->AP_SPI2;SPI3->AP_SPI3;
{REG_PIN_IIC_MATRIX_MTX_CFG,0x6A270100},//IIC0->AP_IIC0; IIC1->AP_IIC1; IIC2->CM4_I3C0; IIC3->AP_IIC3; IIC4->AP_IIC4; IIC5->CM4_I3C1; IIC6->AON_IIC1; IIC7->AON_IIC0;




{REG_PIN_EMMC_RST,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_RST,                 BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//EMMC_RST
{REG_PIN_EMMC_CMD,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_CMD,                 BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_CMD
{REG_PIN_EMMC_D0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D0,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D0
{REG_PIN_EMMC_D3,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D3,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D3
{REG_PIN_EMMC_D2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D2,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D2
{REG_PIN_EMMC_D5,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D5,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D5
{REG_PIN_EMMC_CLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_CLK,                 BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//EMMC_CLK
{REG_PIN_EMMC_DS,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_DS,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//EMMC_RCLK
{REG_PIN_EMMC_D1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D1,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D1
{REG_PIN_EMMC_D4,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D4,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D4
{REG_PIN_EMMC_D6,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D6,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D6
{REG_PIN_EMMC_D7,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D7,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D7
{REG_PIN_CHIP_SLEEP,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_CHIP_SLEEP,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CHIP_SLEEP
{REG_PIN_AUD_ADSYNC,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_ADSYNC,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//AUD_ADSYNC
{REG_PIN_DCDC_ARM1_EN,                  BITS_PIN_AF(0)},
{REG_MISC_PIN_DCDC_ARM1_EN,             BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCPU1_EN
{REG_PIN_PTEST,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_PTEST,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//GND
{REG_PIN_AUD_DASYNC,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_DASYNC,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_DASYNC
{REG_PIN_LCM_RSTN,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_LCM_RSTN,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//LCM_RSTN
{REG_PIN_AUD_SCLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_SCLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_SCLK
{REG_PIN_DSI_TE,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_DSI_TE,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//LCM_FMARK
{REG_PIN_AUD_ADD0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_ADD0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//AUD_ADD0
{REG_PIN_DCDC_ARM0_EN,                  BITS_PIN_AF(0)},
{REG_MISC_PIN_DCDC_ARM0_EN,             BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCPU0_EN
{REG_PIN_ADI_D,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_ADI_D,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//ADI_D
{REG_PIN_XTL_EN1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_XTL_EN1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_CM4|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_XTL_EN1
{REG_PIN_XTL_EN0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_XTL_EN0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AUDCP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//NC
{REG_PIN_AI_EN,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_AI_EN,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDAI_EN
{REG_PIN_CLK_32K,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CLK_32K,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//APPMIC_AP_32K
{REG_PIN_EXT_RST_B,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_EXT_RST_B,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//EXT_RST_B
{REG_PIN_ANA_INT,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_ANA_INT,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//ANA_INT
{REG_PIN_AUD_DAD1,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_DAD1,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_DAD1
{REG_PIN_ADI_SCLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_ADI_SCLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//ADI_SCLK
{REG_PIN_AUD_DAD0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_DAD0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_DAD0
{REG_PIN_SIMCLK2,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_SIMCLK2,                  BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C4_SCL
{REG_PIN_SIMDA2,                        BITS_PIN_AF(1)},
{REG_MISC_PIN_SIMDA2,                   BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C4_SDA
{REG_PIN_SIMRST2,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMRST2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//UCP1301_RSTN
{REG_PIN_SIMCLK0,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMCLK0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_SIMDA0,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMDA0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_SIMRST0,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMRST0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_SIMCLK1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMCLK1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_SIMDA1,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMDA1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_SIMRST1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMRST1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_SD0_D_3,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_3,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D3
{REG_PIN_SD0_D_2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_2,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D2
{REG_PIN_SD0_CMD,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_CMD,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_CMD
{REG_PIN_SD0_D_0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_0,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D0
{REG_PIN_SD0_D_1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_1,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D1
{REG_PIN_SD0_CLK,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_CLK,                  BITS_PIN_DS(6)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//TF_SD0_CLK0
{REG_PIN_SD2_CMD,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_CMD,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_CMD
{REG_PIN_SD2_D_0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D_0,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D0
{REG_PIN_SD2_D_1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D_1,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D1
{REG_PIN_SD2_CLK,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_CLK,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_CP_SD2_CLK
{REG_PIN_SD2_D_2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D_2,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D2
{REG_PIN_SD2_D_3,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D_3,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D3
{REG_PIN_RFCTL_0,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_0,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D4
{REG_PIN_RFCTL_1,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_1,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D5
{REG_PIN_RFCTL_2,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_2,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D6
{REG_PIN_RFCTL_3,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_3,                  BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CP_SD2_D7
{REG_PIN_RFCTL_4,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_4,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_CP_SD2_DS
{REG_PIN_RFCTL_5,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_5,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//AP_I2S3_SDI
{REG_PIN_RFCTL_6,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_6,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_I2S3_SDO
{REG_PIN_RFCTL_7,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_7,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_I2S3_LRCK
{REG_PIN_RFCTL_8,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_8,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//AP_I2S3_SCLK
{REG_PIN_RFCTL_9,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_9,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//APPMIC_CPPMIC_32K
{REG_PIN_RFCTL_10,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_10,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CP_VDDMODEM_EN
{REG_PIN_RFCTL_11,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_11,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_CP_GPIO0
{REG_PIN_RFCTL_12,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_12,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC(GPIO31)
{REG_PIN_RFCTL_13,                      BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_13,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//LCM_BL_PWM(GPIO32)
{REG_PIN_RFCTL_14,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_14,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_CP_GPIO3(GPIO33)
{REG_PIN_RFCTL_15,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_15,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_CP_GPIO4(RFCTL16)
{REG_PIN_RFCTL_16,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_16,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_CP_GPIO5(RFCTL_17)
{REG_PIN_RFCTL_17,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_17,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC(GPIO9)
{REG_PIN_RFCTL_18,                      BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_18,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_U3TXD(RFCTL19)
{REG_PIN_RFCTL_19,                      BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_19,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_U3RXD(RFCTL20)
{REG_PIN_DTDO,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_DTDO,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//SUBPMIC_NIRQ(TDO_LTE)
{REG_PIN_DTDI,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_DTDI,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//SUBPMIC_GPIO2(TDI_LTE)
{REG_PIN_DTMS,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_DTMS,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//TOF_GPIO(TMS_LTE)
{REG_PIN_DTCK,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_DTCK,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//TOF_XSHUT(TCK_LTE)
{REG_PIN_DRTCK,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_DRTCK,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC(RTCK_LTE)
{REG_PIN_U2TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U2TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_U2TXD
{REG_PIN_U2RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U2RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_U2RXD
{REG_PIN_SCL6,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL6,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C6_SCL
{REG_PIN_SDA6,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA6,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C6_SDA
{REG_PIN_MTCK_ARM,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_MTCK_ARM,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_MTCK
{REG_PIN_MTMS_ARM,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_MTMS_ARM,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_MTMS
{REG_PIN_U0TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U0TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CP_U0RXD
{REG_PIN_U0RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U0RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//CP_U0TXD
{REG_PIN_U0CTS,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_U0CTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//LCM_ID(CP_U0RTS)
{REG_PIN_U0RTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U0RTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//NC(CP_U0CTS)
{REG_PIN_USB30_SW,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_USB30_SW,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//USBSW_EN
{REG_PIN_RFSCK0,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_RFSCK0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFSDA0,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_RFSDA0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFSEN0,                        BITS_PIN_AF(1)},
{REG_MISC_PIN_RFSEN0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_CP_PCIE_WAKE
{REG_PIN_RFSCK1,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_RFSCK1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFSDA1,                        BITS_PIN_AF(1)},
{REG_MISC_PIN_RFSDA1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_CP_PCIE_RST
{REG_PIN_RFSEN1,                        BITS_PIN_AF(1)},
{REG_MISC_PIN_RFSEN1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_CP_PCIE_CLKREQ
{REG_PIN_RF_LVDS0_ADC_ON,               BITS_PIN_AF(3)},
{REG_MISC_PIN_RF_LVDS0_ADC_ON,          BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RF_LVDS0_DAC_ON,               BITS_PIN_AF(3)},
{REG_MISC_PIN_RF_LVDS0_DAC_ON,          BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFFE0_SCK,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE0_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_CP_GPIO1
{REG_PIN_RFFE0_SDA,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE0_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_CP_GPIO2
{REG_PIN_RFFE1_SCK,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE1_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CPPMIC_PBINT
{REG_PIN_RFFE1_SDA,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE1_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//AP_CPPMIC_RST
{REG_PIN_SCL2,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL2,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C2_SCL
{REG_PIN_SDA2,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA2,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C2_SDA
{REG_PIN_KEYOUT_0,                      BITS_PIN_AF(2)},
{REG_MISC_PIN_KEYOUT_0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//AG_INT0
{REG_PIN_KEYOUT_1,                      BITS_PIN_AF(2)},
{REG_MISC_PIN_KEYOUT_1,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//PROX_INT
{REG_PIN_KEYOUT_2,                      BITS_PIN_AF(2)},
{REG_MISC_PIN_KEYOUT_2,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//AG_INT1
{REG_PIN_KEYIN_0,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYIN_0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//KEYIN0
{REG_PIN_KEYIN_1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYIN_1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_KEYIN_2,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYIN_2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WB_RST
{REG_PIN_SPI3_DO,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI3_DO,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//BOARD_ID3
{REG_PIN_SPI3_CSN,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI3_CSN,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_SPI3_CLK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI3_CLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCAMA_EN
{REG_PIN_SPI3_DI,                       BITS_PIN_AF(2)},
{REG_MISC_PIN_SPI3_DI,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_CM4|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WF_HOST_WAKE
{REG_PIN_U1TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U1TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_U1TXD
{REG_PIN_U1RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U1RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_U1RXD
{REG_PIN_SPI_TE,                        BITS_PIN_AF(1)},
{REG_MISC_PIN_SPI_TE,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//WF_WAKE_HOST
{REG_PIN_PWMC,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_PWMC,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WB_CHIP_EN
{REG_PIN_EXTINT0,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_EXTINT0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//CTP_INT
{REG_PIN_EXTINT1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_EXTINT1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CTP_RST
{REG_PIN_SDA3,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA3,                     BITS_PIN_DS(3)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//CTP_SDA
{REG_PIN_SCL3,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL3,                     BITS_PIN_DS(3)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//CTP_SCL
{REG_PIN_SPI0_CSN,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_SPI0_CSN,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//FTID_SPI_CS
{REG_PIN_SPI0_DO,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SPI0_DO,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//FTID_SPI_DI
{REG_PIN_SPI0_DI,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SPI0_DI,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//FTID_SPI_DO
{REG_PIN_SPI0_CLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_SPI0_CLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//FTID_SPI_CLK
{REG_PIN_EXTINT9,                       BITS_PIN_AF(2)},
{REG_MISC_PIN_EXTINT9,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//TF_DET
{REG_PIN_EXTINT10,                      BITS_PIN_AF(2)},
{REG_MISC_PIN_EXTINT10,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BAT_DET
{REG_PIN_IIS1DI,                        BITS_PIN_AF(2)},
{REG_MISC_PIN_IIS1DI,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//FTID_INT
{REG_PIN_IIS1DO,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS1DO,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//FTID_RSTN
{REG_PIN_IIS1CLK,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS1CLK,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//SUBPMIC_BUCK_NIRQ
{REG_PIN_IIS1LRCK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS1LRCK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//DCDC_NIRQ
{REG_PIN_SCL7,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL7,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C7_SCL
{REG_PIN_SDA7,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA7,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C7_SDA
{REG_PIN_SPI2_CSN,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI2_CSN,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//EAR_CTL2
{REG_PIN_SPI2_DO,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_SPI2_DO,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//CP_DCDC_NIRQ
{REG_PIN_SPI2_DI,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI2_DI,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//USB_LDO_EN
{REG_PIN_SPI2_CLK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI2_CLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//EAR_CTL1
{REG_PIN_SCL0,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL0,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C0_SCL
{REG_PIN_SDA0,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA0,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C0_SDA
{REG_PIN_SDA1,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA1,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C1_SDA
{REG_PIN_SCL1,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL1,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C1_SCL
{REG_PIN_CMMCLK0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CMMCLK0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_MCLK0
{REG_PIN_CMMCLK1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CMMCLK1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_MCLK1
{REG_PIN_CMRST0,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST0
{REG_PIN_CMRST1,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST1
{REG_PIN_CMPD0,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD0,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_PWDN0
{REG_PIN_CMPD1,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD1,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_PWDN1
{REG_PIN_CMMCLK2,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_CMMCLK2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAMERA_FLASH_EN
{REG_PIN_CMPD2,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD2,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_PWDN2
{REG_PIN_CMRST2,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST2,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST2
{REG_PIN_IIS0DI,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0DI,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//BT_PCM_OUT
{REG_PIN_IIS0DO,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0DO,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BT_PCM_IN
{REG_PIN_IIS0CLK,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0CLK,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//BT_PCM_CLK
{REG_PIN_IIS0LRCK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0LRCK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//BT_PCM_SYNC
{REG_PIN_U5TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U5TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_CM4|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BB_U3RXD
{REG_PIN_U5RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U5RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BB_U3TXD
{REG_PIN_CLK_AUX0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_CLK_AUX0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WCN_32K_IN
{REG_PIN_MEMS_MIC_CLK0,                 BITS_PIN_AF(0)},
{REG_MISC_PIN_MEMS_MIC_CLK0,            BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//PDM_CLK0
{REG_PIN_MEMS_MIC_DATA0,                BITS_PIN_AF(0)},
{REG_MISC_PIN_MEMS_MIC_DATA0,           BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//PDM_DATA0
{REG_PIN_MEMS_MIC_CLK1,                 BITS_PIN_AF(3)},
{REG_MISC_PIN_MEMS_MIC_CLK1,            BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//WB_INT
{REG_PIN_MEMS_MIC_DATA1,                BITS_PIN_AF(3)},
{REG_MISC_PIN_MEMS_MIC_DATA1,           BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_U4TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//GPS_U1RXD
{REG_PIN_U4RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//GPS_U1TXD
{REG_PIN_U4CTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4CTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//GPS_U1RTS
{REG_PIN_U4RTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4RTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//GPS_U1CTS
{REG_PIN_U7TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U7TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BT_U0RXD
{REG_PIN_U7RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U7RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BT_U0TXD
{REG_PIN_U7CTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U7CTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BT_U0RTS
{REG_PIN_U7RTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U7RTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//BT_U0CTS
{REG_PIN_SD1_CLK,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_SD1_CLK,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AP_WCN_PCIE_RST
{REG_PIN_SD1_CMD,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_CMD,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//BOARD_ID0
{REG_PIN_SD1_D_0,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_D_0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//BOARD_ID1
{REG_PIN_SD1_D_1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_D_1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//BOARD_ID2
{REG_PIN_SD1_D_2,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_SD1_D_2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_WCN_PCIE_CLKREQ
{REG_PIN_SD1_D_3,                       BITS_PIN_AF(1)},
{REG_MISC_PIN_SD1_D_3,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//AP_WCN_PCIE_WAKE
{REG_PIN_ESE_GPIO,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_ESE_GPIO,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESE_SWP,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_ESE_SWP,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_CSN,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_CSN,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_CLK,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_CLK,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D7,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D7,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D6,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D6,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D5,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D5,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D4,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D4,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D3,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D3,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D2,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D2,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D1,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D1,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_ESESPI_D0,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_ESESPI_D0,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC


};

/*here is the adie pinmap such as 2730*/
static pinmap_t adie_pinmap[]={
{REG_PIN_ANA_EXT_XTL_EN0,               BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_IE},//CP_XTL_EN_V3
{REG_PIN_ANA_EXT_XTL_EN1,               BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BITS_ANA_PIN_AF(1)|BIT_ANA_PIN_SLP_OE},//BAT_DET
{REG_PIN_ANA_EXT_XTL_EN2,               BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_IE},//AP_XTL_EN1
{REG_PIN_ANA_EXT_XTL_EN3,               BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_IE},//WB_CLK_EN1
{REG_PIN_ANA_PTESTO,                    BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BITS_ANA_PIN_AF(1)|BIT_ANA_PIN_SLP_IE},//CP_XTL_EN_NR
{REG_PIN_ANA_DCDC_GPU_EN,               BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BITS_ANA_PIN_AF(1)|BIT_ANA_PIN_SLP_IE},//CP_XTL_EN_BB
};



int  pin_init(void)
{
	int i;
	for (i = 0; i < sizeof(pinmap)/sizeof(pinmap[0]); i++) {
		__raw_writel(pinmap[i].val, CTL_PIN_BASE + pinmap[i].reg);
	}

	for (i = 0; i < sizeof(adie_pinmap)/sizeof(adie_pinmap[0]); i++) {
		sci_adi_set(CTL_ANA_PIN_BASE + adie_pinmap[i].reg, adie_pinmap[i].val);
	}

	pin_uart_port_cfg();

	return 0;
}
